LORIS – Laboratory for Robust Information Systems

5 new journal papers are published

September 7, 2016September 14, 2016

LORIS group recently published 5 new journal articles, on topics ranging from efficient file synchronization (Sala, Schoeny, Bitouze, Dolecek, TCOM, June 2016), to LDPC codes for multi-level Flash and modern HDDs (Hareedy, Lanka, Dolecek, JSAC, Sept. 2016) and (Hareedy, Amiri, Galbraith, Dolecek, TCOM, Aug. 2016), and to spatially coupled codes...

Post-doc positions available!

August 10, 2016September 14, 2016

2 postdoc positions available in Prof. Lara Dolecek's research group at UCLA, starting this fall. We are looking for talented students who want to work on one of the following: 1. Coding theoretic methods and algorithms for emerging memories and modern computing systems 2. New algorithms and coding-theoretic techniques for...

Two papers at SELSE and both of our papers received “Best of SELSE” Award !

May 12, 2016May 12, 2016

LORIS group has two papers at SELSE conference and both papers have received Best-Of-SELSE Award "Software Defined Error-Correcting Codes" joint work by Mark Gottscho (nanoCAD UCLA), Clayton Schoeny (LORIS), L. Dolecek, and Prof. Puneet Gupta (nanoCAD PI, UCLA) "A Unified Framework for Error Correction Techniques in On-Chip Memories," joint work...

Monograph on Channel Coding Methods for Non-Volatile Memories is Published

May 11, 2016May 18, 2016

Our monograph is published by Foundations and Trends in Information and Communications Theory, February 2016 issue. Link to the monograph is here: Abstract of the monograph: Non-volatile memories (NVMs) have emerged as the primary replacement of hard-disk drives for a variety of storage applications, including personal electronics,...

Clayton Schoeny in a winning pair of a $100k 2016 Qualcomm Innovation Fellowship!

May 11, 2016September 7, 2016

Congratulations to Clayton Schoeny and Mark Gottscho for being selected as Qualcomm Innovation Winners for their project "Software-defined ECC"! Clayton and Mark are one of only 8 winning teams nationwide (with 6% overall acceptance rate). List of winners is here. Full-feature UCLA article is here.

Events

(Sept. 2016) Prof. Lara gives a plenary talk on mathematical techniques for robust computing

Prof. Lara gave an invited plenary talk on new coding theoretic techniques for robust computing at the 2016 IEEE Turbo Coding Symposium in Brest, France. More information is on the conference website https://conferences.telecom-bretagne.eu/turbocodes/invited-speakers/

(August 2016) LORIS in Silicon Valley at Leading Conferences

PhD student Homa Esfahanizadeh presents our group's work on modern graph based codes for Flash at the 2016 Flash Memory Summit in Santa Clara, CA. Prof. Lara presents our research on spatially coupled codes for data storage at The Magnetic Recording Conference (TMRC) at Stanford University.

(June/July 2016) Upcoming conferences: 2 papers at DSN and 2 papers at ISIT

LORIS team will present 1) new research results on software-defined ECC and 2) new research results on a unified framework for error correction techniques in on-chip memories at the IEEE International Conference on Dependable Systems and Networks (DSN). LORIS team will present two papers at the IEEE International Symposium on...

(April 2016) Seminar at Texas A&M University on Coding Theory for Robust Computing

Prof. Dolecek gave a seminar talk on LORIS Research on coding theoretic-mehods for modern computing in ECE Seminar at Texas A&M University.

(April 2016) Presentation at Approximate Computing Workshop

We presented a survey on information/coding-theoretic methods at 2016 WAX. More information is available here.

(March 2016) Paper at DATE 2016 on an Energy-Efficient Decoder

In a collaboration with Prof. Norbert Wehn's group at UKL, Germany, we developed a new energy-efficient LDPC decoder. Voltage scaling scheduling is executed based on a new theoretical analysis. ASIC implementation at UKL demonstrates up to 40% energy savings over the nominal case.

LORIS laboratory works on developing mathematical tools and techniques for a broad range of modern data storage and memory technologies, future computing systems, and new data science applications. For more information see RESEARCH PAGES.

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